1. Field of the Invention
The present invention relates to phase detectors, and in particular, to sampling phase detectors.
2. Related Art
Referring to FIG. 1, the classical phase-locked loop (PLL) 10 has an architecture as shown with a phase frequency detector and charge pump 12, a low pass filter 14, a voltage controlled oscillator (VCO) 16, and a frequency divider 18 with divider ratio N, all interconnected substantially as shown. As is well known, the divider 18 in the feedback loop is used to provide frequency down conversion to ensure a correct frequency relationship between the input reference signal 11 and the output signal 17. While useful and widely used, such an architecture has two basic limitations: tradeoff between loop noise and VCO noise; and multiplication of loop phase noise power by the square of the divider ratio (N2) transferred to the output.
Referring to FIG. 2, an alternative PLL architecture 20 uses a sampling phase detector and charge pump 22, thereby avoiding the need for a feedback frequency divider. The VCO output signal 17 is sub-sampled by the reference clock 11. Such sampling phase detectors are well known, and are often used in clock data recovery (CDR) circuits and delay locked loop (DLL) circuits.
Referring to FIG. 3, such a PLL architecture 20 performs sub-sampling with a sample-and-hold (S&H) circuit 22a, the primary elements of which (in its most simplified representation) are a serial switch circuit 24 and shunt capacitance 26. By avoiding the use of a feedback frequency divider, the frequency divider noise is eliminated.
Referring to FIG. 4, in such a sub-sampling process, the sine wave VCO output signal 17 with frequency fVCO is sampled by pulses with the clock signal 11 frequency fref, where fVCO=N*fref. With an integer ratio N, the sub-sampler output voltage 23 should ideally be a constant DC voltage Vsam.
Referring to FIGS. 3A and 4A, in accordance with a more practical implementation, the S&H circuit 22b includes serial switch circuits 24a, 24b and with the shunt capacitance implemented as two capacitors 26a, 26b. The VCO output signal 17 is sampled by non-overlapping reference clock signals 11p, 11n such that the VCO output signal 17 is sampled by the first clock signal 11p and the first sampled signal 23a is sampled by the second clock signal 11n to produce the final sub-sampler output voltage 23 with a constant DC voltage Vsam when fOSC=N*fref.
Such conventional sampling phase detectors, however, have their own disadvantages. For example, one property of a sampling phase detector is a large detection gain. In order to use it in a feedback loop like a DLL or PLL and ensure loop stability, either the performance of the phase detector must be sacrificed or an external loop filter with a low bandwidth, and, therefore, large capacitances, must be used. Such an external loop filter, of course, generally prevents such a phase detector from being fully integrated on a chip.